Siemens Questa Formal Security Engineer Jobs: Browse IC Security Roles
Hardware security teams increasingly lean on formal methods to prove that a chip keeps trusted and untrusted logic apart, and Siemens Questa Formal sits in the middle of that work. These roles are for verification engineers who use Questa Formal's security apps, including information flow tracking and access control property checking, to show that security-sensitive silicon enforces separation the way the spec demands.
Day to day you write SystemVerilog Assertions for security properties, run Questa Sec to trace information flow, and build verification plans that cover the hardware root of trust, cryptographic accelerator correctness, and privilege level enforcement. The bar is exhaustive proof, not vector coverage. A property like "this key is never observable at that output" has to hold across every legal state, not just the ones a testbench happened to hit.
The work overlaps closely with formal verification engineer openings and IC security design roles, and many engineers move between them as programs shift from architecture to sign-off.
Demand is climbing fastest in automotive, IoT, payment, and AI inference silicon, where a security gap carries certification or liability weight. Questa Formal safety apps also back ISO 26262 work, so automotive programs value engineers who can prove that lockstep comparison logic and ECC detection behave correctly under fault injection. Before you apply, it helps to know whether a company runs a Cadence-primary, Synopsys-primary, or mixed-vendor flow, since that shapes the tool set you will actually use.
Formal and security specialists sit near the top of the verification pay band because the skill is scarce and hard to fake. The semidesignjobs salary guide breaks down how tool-specific expertise shifts total compensation across levels.
Save a search on semidesignjobs.com for Questa Formal and security verification, and you will get an email when a matching role opens instead of refreshing careers pages.
FAQ
What is information flow tracking in Questa Formal security verification
Information flow tracking uses formal methods to verify that sensitive data, such as cryptographic keys, personal information, and secure boot measurements, cannot reach untrusted outputs or be observed by unauthorized logic. Questa Sec taints the sensitive sources and then formally proves the taint label never propagates across the trust boundary points you specify.
How does Questa Formal support ISO 26262 safety verification in automotive IC design
Questa Formal ships safety apps that verify the behavior of safety mechanisms: dual-core lockstep comparison logic, ECC error detection and correction, CRC checkers, and hardware monitors. The formal proofs show these mechanisms detect or correct every specified fault category, which feeds the safety case documentation an ISO 26262 ASIL certification requires.
What separates simulation-based security testing from formal security verification
Simulation only confirms that the specific attack scenarios you wrote fail. Formal security verification proves that no attack within the formal model can violate a property at all. For a claim like "secret key X is never observable at output Y," formal proof gives assurance that no number of test vectors in simulation can match.