RF IC Design Engineer Jobs: Find Radio Frequency Chip Roles
The frontend of every wireless chip starts with an RF IC engineer's work: the low-noise amplifier, mixer, power amplifier, and frequency synthesizer that convert antenna signals to baseband and back. These circuits operate at microwave and millimeter-wave frequencies, where layout parasitics that would be negligible at audio rates matter enormously, and a dB of excess noise figure can blow a link budget.
Three major technology waves are running simultaneously: Wi-Fi 7 across 2.4, 5, and 6 GHz bands; 5G NR FR2 mmWave at 28, 39, and 60 GHz; and LEO satellite broadband from programs like SpaceX Starlink. All three are generating sustained hiring demand for engineers who can design and tape out RF ICs.
Core skills include S-parameter characterization and noise-figure optimization, EM simulation with Ansys HFSS or Cadence AWR to model inductors, transmission lines, and bondwires, layout parasitic extraction and back-annotation, and post-layout harmonic balance or transient simulation. CMOS is the dominant technology for sub-6 GHz transceivers because of integration density and cost. SiGe BiCMOS handles mmWave power amplifiers and LNAs where transistor fT above 200 GHz is required. This work closely overlaps with analog IC design engineer roles and PLL design engineer jobs, since frequency synthesis underpins every transceiver architecture.
Qualcomm and MediaTek drive high-volume 5G and Wi-Fi SoC hiring across San Diego, Singapore, and Taipei. Apple's in-house RF team designs the UWB and cellular frontend ICs in iPhone and Apple Watch. Analog Devices, Qorvo, and MACOM focus on defense radar, satellite, and mmWave infrastructure. NXP and Infineon cover 77 GHz automotive radar. Most openings are on-site or hybrid, since RF measurement requires lab access to vector network analyzers, spectrum analyzers, and probing stations.
Compensation for mid-career RF IC engineers in the US typically runs $130K to $180K base. Staff and principal engineers at flagship 5G programs at Qualcomm or Apple regularly see total comp above $200K. Check the semiconductor salary guide for current market ranges by level and geography.
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FAQ
What process technologies are used in RF IC design engineer jobs?
CMOS and SiGe BiCMOS are the two main options. CMOS is preferred for integrated transceivers at sub-6 GHz because of cost and integration density. SiGe BiCMOS is used for mmWave and high-performance analog applications where transistor fT and fMAX values are the binding constraint, such as 28 GHz or 77 GHz front-end modules.
What is the role of EM simulation in RF IC design?
EM simulation tools like Ansys HFSS or Keysight Momentum model passive structures, including inductors, transmission lines, bondwires, and package parasitics, at RF frequencies where lumped-element models break down. Results are back-annotated into the circuit simulator for accurate pre-silicon performance prediction, reducing the risk of costly respins.
How does 5G mmWave design differ from sub-6 GHz RF IC design?
MmWave design at 24 to 40 GHz faces much higher path loss, requiring phased array beamforming with multiple RF chains per antenna, which is a fundamentally different system architecture from sub-6 GHz. Circuit design challenges include achieving sufficient gain with available transistor fT and managing electromagnetic coupling in compact phased arrays.