Mid-Level DFT Engineer Positions: Browse Test Design Roles
A mid-level DFT engineer owns the test logic for a block or subsystem end to end: scan insertion, ATPG, pattern signoff, and a clean handoff to physical design and the ATE team. Companies expect 3 to 7 years of design-for-test work and the judgment to make architecture calls without a senior engineer checking every step.
At this level you run ATPG in one major tool set, usually Siemens Tessent or Synopsys TestMAX, and deliver a DFT netlist that meets both fault coverage and timing targets. You generate stuck-at and transition patterns, chase down uncovered faults in non-observable sequential logic, and feed scan chain ordering back to physical design so routing overhead stays low.
Memory BIST and JTAG (IEEE 1149.1) experience widens the range of roles open to you. Boundary scan matters for board-level test and field debug, so engineers who can implement and verify it tend to see more mid-level DFT openings.
Test cost is a constant pressure. Scan compression with Tessent TestKompress or TestMAX DFTMAX cuts pattern volume and ATE time, and hierarchical DFT lets you reuse block-level patterns at the top level. Knowing when to push compression ratios and when they start eroding coverage is the kind of call that separates mid-level work from junior scan insertion.
Qualcomm, Broadcom, Marvell, Nvidia, AMD, and Intel all staff dedicated DFT teams, and many fabless SoC shops fold DFT into the physical design group. Mobile SoC and data center accelerator programs carry the heaviest test demands, since high pin counts and large memory arrays make BIST and compression strategy a first-order concern.
Mid-level DFT compensation in the US generally runs about $130K to $175K base, with total comp reaching $160K to $210K once bonus and stock are included. Location and segment move the numbers, so check the salary guide for semiconductor jobs before you negotiate.
The general DFT engineer category covers roles across seniority, and senior DFT engineer positions are the next step up, with full chip-level DFT ownership.
Save a search for mid-level DFT engineer positions on semidesignjobs.com and you will get an email when a role matching your tool stack opens.
FAQ
What ATPG metrics are expected from a mid-level DFT engineer
You should be able to run Synopsys TetraMAX or Siemens FastScan ATPG to generate stuck-at and transition fault patterns, then read the resulting fault coverage reports. Spotting uncovered faults caused by non-observable or uncontrollable sequential logic, and proposing fixes to raise coverage, is a core mid-level responsibility.
How does mid-level DFT engineering interact with physical design
You hand the physical design team scan chain ordering and grouping to keep routing overhead down, confirm that DFT insertion did not create new timing violations, and review floorplanning for scan access point placement. Tight coordination on scan routing is what lets a block hit both fault coverage and timing goals.
What is boundary scan (JTAG) and why does it matter at this level
Boundary scan (IEEE 1149.1 JTAG) is a serial test interface for checking chip I/O connectivity and enabling debug access. Mid-level DFT engineers who implement and verify JTAG boundary scan extend the testability and debug reach of their chips, which pays off in board-level PCB test and field debug.