Cadence JasperGold Connectivity Verification Engineer Jobs

Wiring errors in a large SoC hide in plain sight. A missing connection or a bus routed to the wrong address range rarely shows up in simulation, because no directed test walks every address and control combination. Cadence JasperGold connectivity verification engineer jobs exist to close that gap: formal engineers who run the JasperGold Connectivity Verification (JCV) app to prove, exhaustively, that every specified connection either exists or does not.

The day-to-day is setup and triage. You bring integrated SoC RTL into JCV, write the connectivity intent that defines which signals should reach which endpoints, run the analysis, and work through the violations it reports. Much of that intent comes from the chip architecture spec or a UVM RAL register model, so the job leans as much on integration knowledge as on formal technique. This role sits next to the full Cadence JasperGold platform, and it directly supports SoC integration engineering, the discipline that owns the connections JCV checks.

JCV is not a replacement for LVS. LVS compares the netlist against the schematic late in the flow; JCV works earlier, at RTL intent level, so connectivity bugs surface before they cost a physical iteration. That earlier feedback is why mature integration teams pull formal connectivity checking into signoff instead of waiting for the netlist.

The work clusters at companies running complex integration programs: mobile SoC teams stitching together dozens of IP blocks, data center and AI accelerator groups with wide memory maps, and automotive parts where a cross-wired interrupt is a safety problem. These are usually Cadence-primary or mixed-vendor shops, so knowing a company's EDA stack before you apply helps you target the roles where your JCV experience actually counts.

Because JCV depends on a clean, complete intent spec, part of the value you bring is knowing the architecture well enough to say what should and should not be connected. In interviews, a concrete case carries the most weight: the connectivity spec you built, a wiring bug JCV caught that simulation had missed, and how you resolved it. That beats a general claim of formal familiarity.

Browse Cadence JasperGold connectivity verification engineer jobs on semidesignjobs.com, and check the semiconductor salary guide to see where formal verification pay lands before you apply.

FAQ

What types of connectivity errors does JasperGold JCV detect

JCV finds missing connections, where a signal that should be driven has no driver, and unintended ones, where a signal drives a net it should not. It also catches connections to the wrong endpoint, such as a bus reaching the wrong address range or instance, plus structural problems like a constant driving an input that should be variable. These checks work at RTL intent level, complementing LVS, which operates on netlist topology.

How does JCV complement UVM simulation for SoC integration verification

UVM simulation confirms that data moves correctly through valid transaction sequences, but limited stimulus rarely exercises every address map combination or every signal connection. JCV formally verifies that each specified connection either exists or does not, so you get exhaustive structural assurance on top of simulation's functional coverage. Teams typically run both: simulation for behavior, JCV for the connectivity corners simulation keeps missing.

What input specifications does JCV require from the integration engineer

JCV needs a connectivity intent specification, a formal description of which signals should connect to which endpoints. Engineers usually derive it from the chip architecture spec or the UVM RAL register model, defining the allowed source and destination for each signal and marking unreachable paths so they are excluded. Writing that specification takes real SoC architecture knowledge, which is why the role blends integration and formal skills.