Vice President, Security Engineering

Job Title

Vice President, Security Engineering

Role Summary

Senior engineering leader responsible for defining technical strategy and delivering commercial hardware security products. Reports to the senior VP of engineering and leads a small, growing team of individual contributors and managers to translate business objectives into executable engineering plans and reliable delivery.

Role focuses on architecture, algorithms, performance and scalability of EDA-style analysis systems, team building and cross‑functional alignment with product and executive stakeholders.

Experience Level

Senior — requires substantial leadership experience (see Requirements). Typical expectation: at least 8 years managing software teams.

Responsibilities

The role combines technical strategy, delivery ownership, team building, and cross‑functional leadership.

• Define and own long‑term technical strategy and architecture for core hardware security engines.
• Review and challenge architectural and algorithmic decisions for high‑performance, memory‑efficient, scalable analysis systems.
• Set technical standards for algorithmic rigor, performance benchmarking, regression testing, and release readiness.
• Own delivery outcomes: correctness, runtime performance, memory footprint, determinism, and debuggability of multi‑threaded and distributed systems.
• Drive predictable execution from research through productization in a commercial EDA environment, balancing research and disciplined engineering.
• Build, mentor, and retain senior engineers, architects, and engineering managers; develop future technical leaders.
• Partner with product and management to translate customer direction into an actionable R&D roadmap and communicate technical risks and tradeoffs to executives and customers.

Requirements

Core qualifications and technical skills required for success in the role.

Must-have

• Minimum ~8 years managing software teams (individual contributors and managers) delivering complex C++ commercial technical applications.
• Expert programming and debugging skills in modern C++ and proficiency with Linux development environments.
• Hands‑on depth in at least one major EDA area (simulation, synthesis, formal verification, equivalence checking, static analysis) with ability to evaluate algorithms and architectural tradeoffs.
• Strong grounding in algorithms and data structures for digital logic analysis and transformation.
• Proven track record building performant, scalable systems (runtime/memory, concurrency, distributed execution) that operate on very large designs.
• Understanding of SoC design and verification flows and how EDA tools are used in production environments; familiarity with RTL/gate‑level simulation and debugging.
• Executive‑level communication skills and ability to articulate risks, tradeoffs, and outcomes to senior leadership and customers.
• Ability to build and mentor senior technical leaders while remaining engaged in architectural and algorithmic design.
• Collaborative management style, ability to operate in a fast‑paced environment with competing priorities.

Nice-to-have

• Familiarity with hardware security analysis or security‑oriented verification tools.
• Experience implementing and verifying SoC designs at RTL or gate level.
• Background in distributed systems or large‑scale EDA tool performance tuning.

Education Requirements

Bachelor’s degree in Computer Science or Electrical Engineering required; MS or PhD preferred.

About the Company

Company: ArterisIP

Headquarters: Montigny-le-Bretonneux, France

Provider of configurable on-chip interconnect IP and network-on-chip (NoC) solutions for system-on-chip (SoC) integration, offering interconnect fabrics, IP blocks, verification tools and engineering support to semiconductor and system companies.