Validation/Verification Engineer, Staff

Role Overview

As a Validation/Verification Engineer at Synopsys, you will focus on ensuring that designs meet all specifications and function as intended. You will collaborate closely with various engineering teams to validate new designs and verify the accuracy and compliance of existing systems.

Experience Level

We are looking for a highly experienced engineer with a minimum of 5 years in the verification field. Expertise in ASIC or related areas is necessary for this role.

Key Responsibilities

• Develop and execute test plans, test benches, and scenarios.
• Collaborate with design and validation teams to ensure comprehensive design coverage.
• Analyze test results and debug any issues found during verification processes.
• Mentor junior engineers and oversee verification activities.
• Document and present verification findings to stakeholders.

Job Requirements

The ideal candidate will possess a strong background in digital design, programming skills in SystemVerilog or VHDL, and proficiency with verification methodologies such as UVM or OVM. Strong problem-solving skills and the ability to work in a fast-paced environment are also essential.

Education Requirements

A Bachelor's degree in Electrical Engineering, Computer Science, or a related field is required, with a Master's degree preferred for this position.