UVM Verification Engineer - Senior Staff

Role Summary

The UVM Verification Engineer will develop and implement detailed verification test plans for memory interface IP, ensuring robust product quality and performance.

Experience Level

Senior Level

Responsibilities

• Develop detailed verification test plans and comprehensive functional coverage models for complex memory interface IP.
• Implement scalable UVM testbench infrastructure and design robust test cases for verifying training firmware functionality on RTL PHY models.
• Collaborate with architecture and implementation teams through technical reviews for project alignment.
• Diagnose and resolve complex verification and debugging challenges using advanced tools.
• Interpret specifications to develop test scenarios that ensure product robustness.
• Research and integrate emerging technologies in virtual prototyping and emulation to enhance verification efficiency.
• Mentor junior engineers and contribute to team knowledge sharing.

Requirements

• Proficiency in SystemVerilog and UVM, with hands-on experience using simulation and debugging tools.
• Strong background in developing verification solutions focused on productivity and performance.
• Expertise in assertion-based verification and coverage analysis techniques.
• Bachelor’s degree or higher in Electrical or Computer Engineering, Computer Science, or a related field.
• Experience with scripting languages for regression and build systems (e.g., Python, Perl, Shell).
• Familiarity with Linux environments and collaborative engineering workflows.
• Knowledge of virtual prototyping, emulation, and C/C++ co-simulation is a strong asset.
• Understanding of LPDDR or other memory interface standards is desirable.

Education Requirements

Bachelor’s degree or higher in Electrical or Computer Engineering, Computer Science, or a related field.