Technical Staff Engineer - Design
MicrochipJob Title
Technical Staff Engineer - Design
Role Summary
The Technical Staff Engineer will design IO, pad rings, and bump patterns for advanced storage and memory controller SoC products in Microchip's Data Center Solutions (DCS) business unit. The role takes designs from concept through production and works with cross-functional teams to meet package and system-level requirements.
Experience Level
Senior — requires extensive experience; the posting indicates 12+ years of related experience.
Responsibilities
Key responsibilities include:
- Plan and construct pad rings and bump patterns, ensuring alignment with package and system constraints.
- Develop, implement, and maintain IO connectivity and pad ring definitions throughout the design cycle.
- Generate and validate physical design handoff deliverables (pad ring DEF files, Verilog netlists, bump maps, implementation data).
- Ensure IO and pad ring designs comply with design standards, package constraints, and implementation best practices.
- Collaborate with Architecture, Product Design, IP Packaging, Implementation, Product Engineering, Technology Development, and Foundry teams to resolve IO/package issues.
- Support verification, emulation, ASIC validation, and silicon debug by analyzing IO issues and driving design improvements.
Requirements
Must-have technical skills and experience:
- Hands-on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs.
- Knowledge of IO library cells, IO standards, and PHY-level IO interfaces such as SerDes, DDR, PCIe, and CXL.
- Experience with IO planning and implementation EDA tools (e.g., Orbit IO, ISP or equivalent).
- Experience generating and validating IO connectivity deliverables for physical design hand-off.
- Understanding of foundation and hard IP views including RTL, LEF, and liberty formats.
- Proficiency in flow automation and scripting using Tcl and/or Python.
- Strong analytical skills and clear written and verbal communication.
Nice-to-have:
- Experience with DFT methodologies (JTAG/Boundary Scan) and post-silicon bring-up/debug for SoC IO validation.
- Exposure to RTL compilation and synthesis flows; familiarity with Verilog/SystemVerilog.
- Familiarity with project management, versioning, and tracking tools such as SVN and JIRA.
Education Requirements
Required: B.S. in Electrical Engineering. Preferred: M.S. in Electrical Engineering. The posting associates the role with 12+ years of related experience.
About the Company
Company: Microchip
Headquarters: Chandler, Arizona, USA
Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.
