Tapeout Mask Design Engineer

Role Summary

NVIDIA is looking for a Tapeout Mask Design Engineer to join its Advanced Technology Group. The role focuses on full-chip DRC verification of test chips and products. This position requires communication skills for collaboration across various design teams within NVIDIA.

Experience Level

This role is targeted for candidates with over 5 years of relevant industry experience, specifically in Mask Design with a preference for full-chip experience.

Responsibilities

• Execute physical layout of custom devices for ATG test-vehicles primarily using the Virtuoso layout tool.
• Identify and debug full-chip DRC violations utilizing verification tools such as Calibre and ICV.
• Collaborate effectively with physical design engineers, directing them on layout fixes for full-chip violations.

Requirements

Candidates must hold a B.S. in Electrical Engineering or Computer Science, or have equivalent experience. A solid understanding of layout concepts in sub-micron CMOS technologies is essential. Proficiency with Cadence's Virtuoso tool and experience in running/debugging with Calibre and ICV are required. Strong interpersonal skills are also needed for effective communication with design teams across NVIDIA.

Education Requirements

B.S. in Electrical Engineering, Computer Science, or a related field (or equivalent experience).