Staff Verification Design Engineer

Job Title

Staff Verification Design Engineer

Role Summary

Work on verification of digital and mixed-signal ASIC blocks and full-chip designs to ensure tape-out quality. The role partners with design teams to define verification strategy, create tests, run regressions, and support post-silicon bring-up and ATE validation.

Embedded in the verification/engineering team in Hyderabad, this role emphasizes practical verification implementation, automation, and debug across RTL, gate-level and AMS domains.

Experience Level

Mid-level; typically requires 3+ years of experience in the semiconductor industry.

Responsibilities

Primary responsibilities focused on verification, automation, and cross-team support:

• Perform block- and chip-level verification at RTL, gate-level, and analog/mixed-signal (AMS).
• Run digital and mixed-signal simulations and apply formal verification techniques.
• Define verification strategy and detailed verification plans with design teams.
• Develop tests, execute regressions, and monitor coverage to meet tape-out quality targets.
• Participate in design and project reviews, providing verification perspectives and schedule/prioritization input.
• Support post-silicon bring-up and debug for bench validation and automated test equipment (ATE).
• Improve verification scalability and portability via environment enhancements and tool automation.

Requirements

Must-have skills and experience:

• 3+ years of experience in the semiconductor industry.
• Hands-on experience with SystemVerilog as a verification language and UVM implementation.
• Experience debugging digital simulation at RTL and gate-level, isolating module- and system-level issues.
• Scripting experience in Python or Perl for automation and flow support.
• Clear understanding of ASIC design flow.
• Strong analytical, synthesis and problem-solving skills.
• Good verbal and written communication skills; able to work independently and in teams.

Nice-to-have:

• Experience setting up UVM environments from scratch.
• Familiarity with VHDL or SystemVerilog RNM.
• Experience automating verification flows with Python/Perl in an industrial setting.
• Analog behavioral model development and verification experience.

Education Requirements

M.S. in Electrical Engineering, Computer Engineering, Computer Science or a related technical field (or higher) is specified.

About the Company

Company: Semtech

Headquarters: Camarillo, California, USA

Semtech Corporation is a high-performance semiconductor company providing IoT systems and Cloud connectivity solutions. The company focuses on delivering innovative technology solutions that support a smarter, more connected, and sustainable planet, with a dedication to quality across infrastructure, industrial, and consumer markets.