Staff to Senior Staff Engineer, DFT

Role Summary

As a Digital IC Design Staff Engineer, you will join the Switch DFT team within the Data Center Engineering business group. The primary role involves owning and implementing DFT solutions for Marvell's Switch products, managing everything from DFT architecture and strategy to post-silicon validation.

Experience Level

Candidates should possess more than 5 years of professional experience in DFT, specifically in digital design and integrity of DFT methodologies.

Responsibilities

• Develop and implement DFT architecture and testability strategies for top-tier Switch products.
• Collaborate with cross-functional teams including Logic Design, Physical Design, and ATE teams for DFT features integration.
• Facilitate post-Si bring up and debugging processes.
• Conduct gate level simulations, ensuring test mode timing constraints and fault models are met.
• Utilize industry-standard tools for test structure insertion, mentoring others in tools such as Mentor and Synopsys.
• Engage in memory BIST generation and verification on RTL/Netlist level.
• Show leadership within the team, taking ownership of projects to ensure successful tapeouts and post-Si ramp-up.

Requirements

Candidates must demonstrate proficiency in DFT methodologies, including knowledge of SCAN, ATPG, JTAG, and MBIST. Strong scripting skills in Perl or Tcl are required, alongside excellent communication and teamwork abilities. Familiarity with IEEE1149.1/6 JTAG standards and experience with ATE debugging is essential.

Education Requirements

A Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field is required for this position.