Role Summary
As a Staff SoC Verification Engineer, you will be responsible for developing and maintaining advanced verification environments at both module and System-on-Chip (SoC) levels, utilizing SystemVerilog and UVM methodologies. This role involves writing complex test sequences, managing functional coverage models, and collaborating closely with design teams to troubleshoot issues in a fast-paced environment.
Experience Level
This is a senior position requiring a minimum of 8 years of experience in digital verification, including at least 4 years focused on constrained-random verification techniques using UVM.
Responsibilities
Your main responsibilities will include:
- Developing SystemVerilog/UVM-based verification environments.
- Writing test sequences and defining functional coverage models for SoC verification.
- Debugging simulation results and resolving design issues in collaboration with design teams.
- Driving advancements in verification methodologies through constrained-random stimulus generation.
- Automating verification workflows using modern EDA tools.
- Ensuring design-test alignment and contributing to quality assurance and release-readiness for new chips.
Requirements
The ideal candidate will possess the following qualifications:
- 8+ years of experience in digital verification, with 4+ years in constrained-random verification using UVM.
- 2+ years in embedded C development.
- Experience in designing verification architecture based on design specifications.
- Strong proficiency in debugging SystemVerilog RTL and conducting root-cause analysis.
- Familiarity with Python or similar scripting languages, and solid experience in Unix/Linux environments.
- Demonstrated ability to lead and mentor teams.
- Experience in cross-functional collaboration and managing project timelines.
Education Requirements
A degree in Electrical Engineering, Computer Engineering, or a related field is preferred, accompanied by relevant work experience in SoC verification.