Staff SOC Engineer, Physical Design

Role Summary

As a Staff SOC Engineer specializing in Physical Design at Synopsys, you will focus on the development and implementation of sophisticated SOC designs using advanced EDA tools. Your primary responsibility will be to oversee the design from the initial Verilog stage through to the final GDS layout.

Experience Level

This position requires seasoned professionals with between 5 to 10 years of hands-on experience in Engineering, specifically in Place & Route domains.

Responsibilities

• Develop and implement SOC designs utilizing Synopsys EDA tools.
• Contribute to turnkey projects while acting as a trusted advisor to design and CAD teams.
• Independently innovate solutions to engineering problems as they arise.
• Set task-level goals and adhere to project schedules.
• Collaborate with cross-functional teams to enhance tool and IP solutions.
• Mentor and provide technical guidance to junior engineers.

Requirements

Applicants must hold a BS/MS/PhD in Electronics Engineering, Electromechanics, or Telecommunications. Proficiency in tools such as Fusion Compiler/ICC2, alongside strong debugging skills and knowledge of P&R, extraction, and verification processes are essential. Additional experience with signoff tools and scripting languages like TCL or PERL is preferred.

Education Requirements

A Bachelor’s, Master’s, or PhD degree in Electronics Engineering, Electromechanics, or Telecommunications is mandatory.