Staff Silicon Design Verification Engineer

Role Overview

As a Staff Silicon Design Verification Engineer at AMD, you will play a vital role in the Central Engineering Group. Your primary responsibility will be to plan, build, and execute the verification of new and existing features for High-Speed IO Protocol IPs such as USB, PCIe, Ethernet, and UFS, ensuring that the final design is free of bugs.

Position Summary

This position requires a strong passion for modern processor architecture and digital design. You will work collaboratively with a team of engineers across various locations, utilizing your excellent communication skills and analytical abilities to resolve complex problems effectively.

Experience Level

This role is geared towards experienced engineers with over 7 years of relevant experience in digital IP verification, particularly with SV, UVM, and formal verification methodologies.

Key Responsibilities

• Independently manage various design verification tasks while providing technical guidance to team members.
• Collaborate with architects, hardware, and firmware engineers to determine new features for verification.
• Create comprehensive test plans that account for feature interactions, including hardware, firmware, and software driver use cases.
• Estimate the time and resources needed for creating new feature tests and necessary adjustments to the test environment.
• Develop directed and random verification tests.
• Debug test failures to identify root causes and collaborate with RTL and firmware engineers to rectify design defects and testing issues.
• Review functional and code coverage metrics to update tests or adjust constraints for random tests to satisfy coverage requirements.

Essential Requirements

• Proficient in IP-level ASIC verification with experience debugging firmware and RTL codes using simulation tools.
• Expert in UVM testbenches and comfortable working in both Linux and Windows environments.
• Strong foundation in Verilog, System Verilog, C, and C++.
• Familiarity with USB, UFS, Ethernet, PCIe, and AXI technologies is advantageous.
• Experience in developing UVM-based verification frameworks and automated workflows in distributed computing environments.
• Knowledge of SystemC and TLM is beneficial, along with scripting languages such as Perl, Ruby, Makefile, and shell scripting.
• Leadership or mentorship experience is a plus.

Education Requirements

A Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering is required.