Staff Physical Design Engineer

Job Title

Staff Physical Design Engineer

Role Summary

Join a physical design team responsible for RTL-to-GDSII implementation and methodology for high-performance processor/SoC designs targeted at server and networking applications. The role focuses on physical implementation, timing and power integrity signoff, and enabling production-quality tapeouts in advanced CMOS process nodes.

The position works cross-functionally with architecture, RTL, and verification teams to influence design decisions, improve physical design flows, and drive automation and methodology improvements.

Experience Level

Senior-level: typically requires several years of professional experience with progressive responsibility and leadership in back-end physical design and verification.

Responsibilities

Key responsibilities include hands-on implementation, leadership in methodology, and cross-functional coordination to deliver complex SoC tapeouts.

• Define and drive long-term physical design capabilities and infrastructure aligned with company technology strategy.
• Perform full RTL-to-GDSII implementation: synthesis, floorplanning, power grid design, place & route, clock tree synthesis, timing closure, and physical verification (DRC/LVS).
• Execute power and signal integrity signoff and ensure EM/IR and timing robustness.
• Ensure successful and timely tapeouts of complex, high-performance SoCs.
• Collaborate with design teams to influence implementation and timing trade-offs; resolve cross-functional conflicts to maintain project momentum.
• Develop and adopt next-generation physical design methodologies, flows, and automation to improve productivity and quality.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Proven experience in back-end physical design and verification with progressive leadership roles.
• Expertise in hierarchical physical design strategies and addressing challenges at advanced process nodes.
• Practical knowledge of ASIC design flow, RTL integration, synthesis, and timing closure.
• Strong familiarity with modern EDA tools and flows used for implementation and signoff.
• Experience with power grid design, place & route, CTS, and physical verification signoff.
• Strong communication and collaboration skills with ability to influence cross-functional teams and stakeholders.
• Must be eligible to access export-controlled technology; employment may require export license review for non-U.S. citizens.

Nice-to-have / preferred:

• Experience in automation and scripting (Makefile, Tcl, Python, Perl) to improve flow robustness.
• Familiarity with static timing analysis (PrimeTime, Tempus), EM/IR analysis tools (PTSI, Voltus, Redhawk, PrimeRail), extraction tools (Quantus, StarRC), and formal/physical verification tools (Formality, Verplex, Calibre, Hercules).
• Experience developing and deploying advanced physical design methodologies and flows.
• Familiarity with AI/ML-driven optimization in physical design tools.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field (with 3–5 years of relevant experience), or a Master’s/PhD in Computer Science, Electrical Engineering, or related field (with 2–3 years of relevant experience). Equivalent professional experience may be accepted in lieu of a formal degree.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.