Staff Physical Design Engineer

Job Title

Staff Physical Design Engineer

Role Summary

Own block-level physical implementation of complex digital blocks and IP for low-power FPGA products at the Pune engineering center, taking designs from netlist to GDSII.

Work closely with RTL, integration, and architecture teams to achieve timing closure and first-pass silicon success.

Experience Level

Senior — approximately 6+ years of hands-on physical design experience in ASIC/SoC or FPGA silicon development.

Responsibilities

Key responsibilities include:

• Own block-level physical design: floorplanning, power planning, placement, clock tree synthesis, routing, and timing closure.
• Drive synthesis and place-and-route flows using industry EDA tools (Synopsys Fusion Compiler / ICC2, Cadence Innovus, or equivalent).
• Perform static timing analysis and closure across PVT corners and modes.
• Execute physical verification and sign-off: DRC, LVS, ERC, antenna checks, and EM/IR analysis.
• Implement low-power techniques (UPF-based power intent, power gating, multi-Vt optimization).
• Collaborate with RTL, DFT, and integration teams to resolve design convergence issues and support ECO cycles.
• Develop and improve flow automation and methodology using scripting (TCL, Python, Perl).
• Support tape-out activities and correlate physical design metrics with post-silicon results.

Requirements

Must-have qualifications and preferred skills:

• Must-have: 6+ years of hands-on physical design experience in ASIC/SoC or FPGA silicon development.
• Must-have: Strong expertise in synthesis, place-and-route, static timing analysis, and physical sign-off on advanced process nodes.
• Must-have: Practical experience with low-power implementation and design convergence at block and subsystem level.
• Must-have: Proficiency in scripting for flow automation (TCL, Python, Perl).
• Must-have: Strong debugging skills, a track record of successful tape-outs, and effective cross-functional communication.
• Nice-to-have: Experience with FPGA or custom silicon physical implementation.
• Nice-to-have: Exposure to EM/IR analysis tools (Ansys RedHawk/Totem) and DFM closure.
• Nice-to-have: Advanced-node experience (16nm and below).

Education Requirements

Bachelor's or Master's degree in Electronics / Electrical Engineering or a related technical field.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.