Staff Performance Modeling Engineer
ArterisIPJob Title
Staff Performance Modeling Engineer
Role Summary
Join an engineering team that designs interconnect and memory-hierarchy solutions for advanced mobile, telecom, automotive, and consumer SoC products. The role models complex, highly configurable designs and delivers performance analyses that inform architectural and microarchitectural decisions.
The position interacts with internal architecture, development, and verification teams and supports customers with performance estimation and analysis solutions.
Experience Level
Senior — 5+ years of relevant experience (performance modeling and architecture analysis).
Responsibilities
Primary responsibilities include:
- Develop and maintain software-based performance models for complex SoC architectures, including interconnects and memory hierarchies.
- Analyze system performance and produce detailed reports to guide architecture and microarchitecture decisions.
- Drive architectural improvements through data-driven performance modeling and analysis.
- Model highly configurable designs using SystemC, C++, and TLM 2.0.
- Collaborate with internal engineering teams across architecture, development, and verification.
- Support customers by providing performance analysis, estimation solutions, and technical expertise.
- Improve modeling methodologies, tools, and workflows.
Requirements
Key qualifications and skills.
- 5+ years developing software performance models for CPUs, GPUs, AI accelerators, Network-on-Chip (NoC), or equivalent systems.
- 5+ years driving architecture and microarchitecture improvements through performance-model analysis.
- Strong experience with SystemC, C++, and TLM 2.0.
- Strong problem-solving, debugging, and analytical skills; ability to evaluate trade-offs and communicate technical insights clearly.
- Proven ability to work effectively in experienced, cross-functional engineering teams.
Preferred / nice-to-have:
- Familiarity with ARM processors and on-chip interfaces such as AXI, AHB, and chip-to-chip interfaces like UCIe and PCIe.
- Knowledge of cache coherency protocols such as CHI.
- Experience with code generators for configurable hardware descriptions.
- Experience with scripting languages such as Python, TCL, or Perl.
- Experience with Platform Architect tools.
Education Requirements
Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent professional experience. The posting also specifies fluency in English and French.
About the Company
Company: ArterisIP
Headquarters: Montigny-le-Bretonneux, France
Provider of configurable on-chip interconnect IP and network-on-chip (NoC) solutions for system-on-chip (SoC) integration, offering interconnect fabrics, IP blocks, verification tools and engineering support to semiconductor and system companies.
