Staff Memory PHY RTL Design Engineer

Role Summary

The Memory PHY team at AMD seeks an experienced Design Engineer specializing in RTL and Firmware development for high-speed LPDDR and DDR IPs. The role involves engaging in the definition, design, and development phases of leading Memory PHYs and interface IP, including creating new I/O designs and enhancing methodologies across multiple designs.

Experience Level

This position requires significant experience in digital design engineering and collaboration with cross-functional teams.

Responsibilities

Key responsibilities include:

• Conducting RTL design for memory I/O.
• Developing PHY digital architecture, from pathfinding to physical implementation.
• Designing, implementing, and verifying PHY link layers.
• Performing digital design and RTL coding.
• Synthesizing timing and driving physical implementation.
• Collaborating with architects and engineers to integrate new features.
• Estimating time for writing feature tests and adapting the testing environment.
• Building unit tests and debugging design failures to resolve root causes.

Requirements

Applicants must have:

• Experience in digital design engineering with proficiency in Verilog, System Verilog, C, and C++.
• Knowledge of synchronization and clocking methodologies.
• Experience with synthesis and timing closure.
• Preferred background in SERDES, DDR, Memory Controller, or MAC Design.
• Proficiency in debugging firmware and RTL code using simulation tools.

Education Requirements

A Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering is required.