Staff Memory Layout Engineer

Role Summary

The Staff Memory Layout Engineer role involves leading the design of advanced memory IP such as SRAM, ROM, and eDRAM. The engineer will work collaboratively to optimize layout designs, ensuring compliance with foundry processes and driving innovation in layout methodologies.

Experience Level

This position requires a minimum of 5 years of experience in layout design, with a strong focus on memory layout technologies.

Responsibilities

Key responsibilities include:

• Leading physical layout design for memory IP at cell and array levels.
• Ensuring compliance with DRC/LVS and memory-specific design constraints.
• Optimizing layouts for area, performance, power, yield, and manufacturability.
• Conducting RC extraction and signal integrity verification for memory arrays.
• Debugging LVS/DRC issues effectively.
• Collaborating with cross-functional teams to ensure successful silicon delivery.
• Mentoring junior engineers and advancing best practices within the team.

Requirements

To be successful in this role, candidates should have:

• Bachelor's or Master’s degree in Electronics Engineering, Telecommunication, Physics, or a related field.
• Proficient understanding of custom layout tools such as Custom Compiler, IC Compiler, and Virtuoso.
• Thorough knowledge of process rules, DRC/LVS protocols, and reliability.
• Experience in debugging and optimizing designs for manufacturability and reliability.

Education Requirements

A Bachelor's or Master's degree in Electronics Engineering, Telecommunications, Physics, or a related field is required.