Staff IP Design Engineer (Functional Safety)

Role Summary

A successful candidate will join a team designing and developing Lattice Foundation IP at Penang to help establish long-term capability in IP-level Functional Safety readiness and product robustness. The candidate will lead research, design and development of safety qualification of Foundation IP and/or safety-relevant aspects of FPGA EDA design flow, ensuring alignment with product, quality and Functional Safety requirements.

Experience Level

The position requires 8+ years of experience in SoC and/or FPGA IP development.

Responsibilities

• Work closely with cross-functional teams to plan and execute Lattice Foundation IP release cycle including requirement analysis, feature scoping, safety impact assessment, development, testing, validation, and release sign-off.

Requirements

• Bachelors, Masters or better in Computer Science, Computer Engineering, Electrical Engineering, or related fields.
• Strong communication skills.
• Knowledge or experience in FPGA architecture and FPGA software tools, specifically for device modeling and soft IP development.
• Hands-on experience in SoC and/or FPGA RTL design, testbench development, logic verification, timing closure, and debugging in accordance with functional safety requirements.
• Demonstrate technical ownership of safety-related SoC and/or FPGA Soft IP development and verification with proven ability to generate audit-ready Functional Safety evidence in compliance with IEC 61508, ISO 26262, or other safety standards.
• Working knowledge of FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related features is a plus.
• Technical leadership and accountability for outcomes across multiple projects.
• Mentorship experience by creating leverage through mentoring engineers and setting technical direction.