Staff IP Design Engineer

Role Summary

The Staff IP Design Engineer will lead technical efforts to build Connectivity IP portfolios for Lattice FPGA. This role involves close collaboration with architects to translate specifications into high-speed RTL designs, focusing on performance, power, and logic utilization.

Experience Level

Senior level with a minimum of 8 years of experience in FPGA or system design.

Responsibilities

Key responsibilities include:

• Building and managing Connectivity IP portfolios.
• Collaborating with architects on RTL design specifications.
• Ensuring optimal performance, power, and logic utilization in designs.
• Leading verification, debug, and timing closure processes.

Requirements

The ideal candidate will possess the following qualifications:

• Experience with high-speed SERDES protocols (e.g., PCIe, Ethernet, CPRI, JESD204B/C).
• Hands-on experience in FPGA RTL design, logic verification, debug, and timing closure.
• Programming skills in languages such as C/C++, Perl, TCL, or Python.
• Knowledge of hardware validation and interoperability testing is a plus.
• Experience with soft IP packaging and testbench development is advantageous.

Education Requirements

BS/MS/PhD in Electronics or Computer Engineering.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.