Staff Engineer - R&D Engineering

Role Overview

As a Staff Engineer in R&D Engineering at Synopsys, you will be tasked with leading the development and deployment of advanced layout methodologies to enhance the efficiency and quality of analog/mixed-signal IP development. Your role focuses on working with global engineering teams, driving collaboration, and ensuring that best practices are integrated into workflows.

Role Summary

We are seeking an experienced engineering leader with a strong background in analog and mixed-signal layout, particularly in advanced CMOS, FinFET, and GAA technologies. You will utilize your expertise to mentor junior engineers while managing multiple projects in a dynamic and collaborative environment.

Experience Requirements

A minimum of 5 years of experience in analog/mixed-signal layout or ASIC physical design, with a preference for candidates who have significant knowledge of FinFET and advanced nodes. Your ability to balance technical skills with leadership and mentoring will be essential for success in this role.

Key Responsibilities

• Define and implement advanced layout methodologies that ensure high-quality outputs.
• Translate customer requirements into clear technical specifications to guide workflow development.
• Develop end-to-end workflows that enhance the consistency and reliability of the design process.
• Collaborate with cross-functional teams to facilitate the adoption of methodologies across various technology nodes.
• Track and analyze performance metrics to promote continuous improvement.
• Create and maintain documentation for methodologies to ensure clarity and usability.
• Engage with both internal teams and external customers as a representative of the Methodology Team.
• Lead innovative efforts in analog/mixed-signal layout flows utilizing both industry-standard tools and proprietary automation solutions.
• Mentor junior staff to foster skill development and knowledge sharing across all levels of the organization.

Essential Skills

• In-depth understanding of analog and mixed-signal CMOS layout principles and chip integration.
• Proficient with industry tools such as Synopsys Custom Compiler and Cadence Virtuoso.
• Proven ability to manage complex projects while ensuring quality and timeliness.
• Strong communication and leadership skills to effectively mentor teams and liaise with diverse stakeholders.

Education Requirements

A relevant engineering degree is required, preferably with a focus on electrical engineering or semiconductor technology.