Staff Engineer - Physical Design and Signoff (Synthesis to GDS2)

Role Summary

We are seeking a skilled Staff Engineer specializing in Physical Design and Signoff processes, particularly focusing on the ASIC design flow from RTL to GDS implementation. This role requires significant hands-on experience in physical verification, static timing analysis (STA), and the challenges associated with advanced semiconductor processes.

Experience Level

This position requires an experienced professional with a minimum of 5+ years in the semiconductor industry, focusing on physical design and signoff methodologies across various advanced nodes.

Responsibilities

The individual will be tasked with the following:

• Conceptualizing and designing RTL to GDS implementations for SLM monitors.
• Creating on-chip monitors for various environmental factors impacting silicon performance.
• Managing digital backend activities such as synthesis and timing closure.
• Executing physical verification tasks including DRC, LVS, and power signoff.
• Collaborating with cross-functional teams to deliver advanced technology solutions.
• Developing new methodologies and refining existing flows for efficiency.

Requirements

The ideal candidate will possess:

• A Bachelor’s or Master’s degree in Electrical Engineering.
• Expertise in physical design, verification, and signoff including DRC, LVS, and STA methodologies.
• Proficient use of EDA tools, particularly Synopsys design tools.
• Demonstrated experience with timing closure and tape-outs on advanced nodes.
• Strong scripting skills in TCL/PERL to enhance design flows.
• A proactive and detail-oriented mindset with effective communication skills.

Education Requirements

BS/B.Tech or MS/M.Tech degree in Electrical Engineering is required.