Staff Engineer - Layout Design Methodology

Role Overview

Seeking a highly skilled Layout Design Methodology Engineer with strong IC layout fundamentals and foundry design rule knowledge. This position focuses on developing robust layout methodologies for high-quality, manufacturable designs. Requires knowledge of device behavior and circuit-layout interaction to influence performance, power, and long-term reliability.

Responsibilities

Analog/Mixed Signal Layout Design & Sign-off

• Apply knowledge of IC layout principles including matching, symmetry, common-centroid, shielding, and noise mitigation.
• Ensure compliance with foundry DRC/LVS/ERC/ANT/DFM rules while optimizing manufacturability and performance.
• Perform and analyze sign-off checks; debug with schematic and design teams, preparing release packages including GDS/OASIS and sign-off reports.

Layout Automation & Productivity Tools

• Develop and maintain automation scripts/tools using Python/Tcl/Perl/SKILL/Shell.
• Create layout productivity tools, and enhance internal layout automation frameworks and methodologies.
• Evaluate and adopt new automation capabilities with EDA vendors.

Cross-functional Collaboration

• Work with design, AMS verification, CAD, and PD teams; mentor junior engineers on layout techniques and automation.
• Present technical reviews and progress updates to global teams.

Experience Level

3–8+ years in IC Layout/Physical Design with successful tapeouts.

Requirements

Must-have

• Experience with EDA Tools: Cadence Virtuoso, Innovus, Mentor/Siemens Calibre.
• Hands-on experience with TSMC/Samsung/UMC foundry PDKs.
• Strong scripting skills in Python/Tcl/Perl/SKILL and shell.
• Solid knowledge of sign-off flow and quality assurance.
• Excellent technical communication skills in English.

Nice-to-have

• Experience with hierarchical/top-level integration and layout automation frameworks.
• Familiarity with Jira/Confluence, Git, and CI/CD workflows.