Staff Engineer, Analog Design (SerDes)

Job Title

Staff Engineer, Analog Design (SerDes)

Role Summary

Design and optimize analog front-end building blocks for SerDes IP and own those blocks from specification through silicon bring-up. The role works on a focused analog design team and collaborates closely with layout, digital RTL, verification, and characterization engineers to deliver production-quality mixed-signal IP.

Your work will target high-speed links used in data centers, AI accelerators, automotive SoCs, and consumer electronics, with an emphasis on performance, power, and first-pass silicon success.

Experience Level

Senior. Typical background: PhD with 2+ years of hands-on SerDes or high-speed analog design experience, or BTech/MTech with 5–10 years in the same domain.

Responsibilities

Primary responsibilities include circuit design, verification, and cross-team integration for SerDes analog blocks.

• Design and optimize analog front-end blocks: drivers, equalizers (CTLE, FFE, DFE), CDRs, PLLs, DLLs, VCOs, phase interpolators, bandgaps, and regulators.
• Run SPICE simulations across PVT corners and build verification testbenches to validate performance against high-speed protocol specifications.
• Collaborate with layout engineers to minimize parasitics, reduce mismatch, and account for proximity and process effects in sub-micron CMOS.
• Work with digital RTL teams to verify calibration loops, adaptation algorithms, and control logic for real-time tuning.
• Present simulation results, design tradeoffs, and performance data in peer reviews and customer technical discussions.
• Document circuit architecture, verification strategies, and test plans for integration into SerDes products.
• Own full lifecycle tasks including post-layout verification, silicon characterization support, and design-for-reliability checks (electromigration, IR drop, aging, ESD).

Requirements

Must-have technical skills and strong domain experience; nice-to-have items noted.

• Silicon-proven experience designing and bringing up analog or mixed-signal blocks in production chips.
• Deep expertise in several SerDes building blocks: analog front-end transceivers, voltage/current-mode drivers, PLLs, DLLs, VCOs, CDRs, CTLE, FFE, DFE, impedance calibrators, serializers/deserializers, or phase interpolators.
• Strong proficiency with SPICE simulation tools and sub-micron CMOS design methodologies, including corner setups, parameter sweeps, and result interpretation.
• Experience optimizing layout for performance: parasitic extraction, device matching, stress effects, and reliability considerations (electromigration, IR drop, aging).
• Familiarity with scripting for automation and simulation flows (TCL, Perl) — strong plus.
• Working knowledge of high-speed serial standards such as PAM4, PCIe 6.0/7.0, Ethernet, USB, SATA, HDMI, or MIPI — highly valued.

Education Requirements

PhD with 2+ years of hands-on SerDes or high-speed analog design experience, or BTech/MTech with 5–10 years in the same domain. Equivalent practical experience is indicated by the posting.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.