Staff EDA Engineer – RTL Front End Tools & Methodologies

Role Summary

This role is for a Staff EDA Engineer specializing in RTL front-end methodologies, power analysis, and simulation tool support. The engineer will work on enabling scalable RTL flows, driving low-power initiatives, and incorporating Generative-AI capabilities into EDA tools.

Experience Level

Senior (9–11 years of experience required, with at least 6 years in RTL front-end EDA tools and methodologies).

Responsibilities

Key responsibilities include:

• Acting as the technical owner for RTL front-end EDA methodologies.
• Driving RTL low-power initiatives and defining power-aware methodologies.
• Enabling RTL power analysis flows using PowerArtist and Joules.
• Providing expert support for RTL simulation and debug.
• Owning SDC constraint understanding and verification.
• Driving the adoption of Generative-AI in EDA workflows.
• Developing and maintaining automation frameworks using Python.
• Collaborating with design and verification teams to resolve issues.
• Serving as the primary interface with EDA vendors.
• Developing methodology documentation and training materials.
• Mentoring junior engineers.

Requirements

Required skills include:

• 9–11 years of experience in EDA tools, RTL front-end methodologies, or CAD engineering roles.
• 5+ years of hands-on experience in RTL power analysis using PowerArtist and Joules.
• Experience driving low-power initiatives at the RTL level.
• Understanding of SDC constraints and front-end timing concepts.
• Strong automation skills in Python programming.
• Problem-solving skills to debug complex issues.

Education Requirements

Not specified.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.