Staff EDA Engineer – RTL Front-End Tools & Methodologies

Job Title

Staff EDA Engineer – RTL Front‑End Tools & Methodologies

Role Summary

Technical lead for RTL front‑end EDA methodologies responsible for enabling scalable, low‑power, and high‑quality RTL flows. The role partners with design, verification, CAD, and EDA vendors to resolve tool issues, define methodology, and deliver automation and documentation.

Hands‑on position based in Pune delivering day‑to‑day project enablement and setting long‑term front‑end EDA strategy, including adoption of generative AI capabilities for EDA workflows.

Experience Level

Senior — 9–11 years total experience with at least 6+ years of deep, hands‑on RTL front‑end EDA tools, flows, and methodologies. Strong domain expertise in RTL power analysis and front‑end tool support.

Responsibilities

Key responsibilities include owning RTL front‑end methods, driving low‑power initiatives, and delivering automation and tool enablement.

• Act as technical owner for RTL front‑end methodologies: simulation, power analysis, and constraint validation.
• Lead RTL low‑power initiatives and enable power‑aware RTL methodologies across projects.
• Enable and support RTL power analysis flows using PowerArtist and Joules; define methodology, debug, and optimize.
• Provide expert support for RTL simulation and debug (QuestaSim, Synopsys VCS, Cadence Xcelium).
• Ensure correctness of SDC constraints and front‑end timing concepts; validate and verify constraints.
• Drive generative‑AI/ML enablement in EDA workflows for log analysis, automation, and productivity improvements.
• Architect, develop, and maintain automation frameworks using Python (with Tcl/Shell as needed) for flow execution, regression, and reporting.
• Serve as primary interface with EDA vendors for issue debug, enhancement requests, version qualification, and roadmap alignment.
• Produce methodology documentation, user guidelines, and training material; mentor junior engineers.

Requirements

Must‑have technical qualifications and role constraints.

• 9–11 years in EDA, RTL front‑end methodologies, or CAD engineering roles.
• 5+ years hands‑on RTL power analysis experience using PowerArtist and Joules.
• Proven experience driving RTL low‑power initiatives and power optimization strategies.
• Solid understanding of SDC constraints, constraint checks, and front‑end timing concepts.
• Advanced automation skills with strong Python proficiency for EDA flow development, analysis, and reporting.
• Experience with RTL simulation and debug tools (QuestaSim, VCS, Xcelium).
• Strong problem‑solving and debugging skills for complex tool, power, and methodology issues.
• Must be based in Pune, India and work from the Pune office four days per week (hybrid, mandatory).

Preferred / nice‑to‑have:

• Experience applying generative‑AI or ML techniques to EDA workflows (log analysis, automation).
• Exposure to RTL quality checks such as lint, CDC/RDC, or power‑intent verification.
• Understanding of how RTL decisions impact synthesis, STA, and physical design.
• Experience working with global, cross‑functional teams and strong communication skills.

Education Requirements

Not specified.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.