Staff Digital Verification Engineer

Role Summary

The Staff Digital Verification Engineer is responsible for utilizing advanced verification methodologies to ensure the functionality and reliability of IP and SoCs. The role demands exceptional technical expertise and adaptability to complex design environments while contributing as an individual contributor.

Experience Level

The ideal candidate should have a minimum of 8 years of experience in digital verification and ASIC design verification, showcasing a strong proficiency in relevant methodologies.

Responsibilities

• Utilize System Verilog for verification, preferably with UVM, while implementing robust verification methodologies.
• Conduct assertion-based verifications and potentially engage in Gate-Level Simulation (GLS).
• Develop and manage environment updates, implement checkers, and create comprehensive test cases.
• Demonstrate ownership of solutions and ensure successful implementation.
• Communicate effectively and proactively with team members and stakeholders.

Requirements

The candidate must possess expertise in verification with a good understanding of complex designs, coupled with excellent debugging skills. Fluency in Verilog RTL coding, along with ASIC design methodologies, is mandatory.

Education Requirements

A Bachelor's degree in Computer Science, Computer Engineering, Electronics, or a related field is required, with a Master's degree preferred.