Staff Digital Design Engineer – CPU Architecture & RISC-V

Role Summary

The Staff Digital Design Engineer will take the technical lead in developing RISC-V-based CPU architecture and integrated subsystems for advanced neuromorphic SoCs. This position involves significant responsibility in guiding design processes from initial specifications to final production sign-off, ensuring robust integration with various system components.

Experience Level

Candidates should have a minimum of 7 years of experience in digital design, specifically within CPU architecture and micro-architecture fields, demonstrating expertise in RISC-V implementations.

Responsibilities

• Design and architect advanced CPU cores and micro-architectures, focusing on RISC-V instruction sets.
• Translate high-level requirements into detailed micro-architectural specifications.
• Collaborate with verification engineers for thorough validation of CPU IP.
• Define and implement SoC architectures, ensuring proper integration of CPU cores with other systems.
• Support SoC verification through top-level testing and robustness assessments.
• Conduct RTL coding and debugging using Verilog/System Verilog.
• Perform both RTL and gate-level simulations to assure design accuracy.
• Carry out all front-end design tasks including synthesis and formal equivalence checking.
• Drive innovative CPU IP concepts from product specifications.
• Integrate third-party CPU IP to optimize system performance.
• Collaborate closely with analog design and verification teams.

Requirements

• Extensive experience in digital design with a strong focus on CPU architecture development.
• Demonstrated success in RISC-V CPU core design, including custom implementations.
• Deep understanding of CPU architectures, pipeline stages, and memory hierarchies.
• Strong proficiency with RTL coding and debugging techniques.
• Experience in SoC architecture and subsystem integration methodologies.
• Solid foundation in digital verification practices and collaborative work with verification teams.
• Familiarity with common CPU communication protocols.

Education Requirements

A relevant degree in Electrical Engineering, Computer Engineering, or a related field is preferred, bolstered by substantial hands-on experience in the design and development of digital systems.