Sr Staff Verification Engineer (数字验证工程师)

Role Summary

The Sr Staff Verification Engineer will focus on understanding design functionality, developing verification environments, and improving verification architecture. The role involves running simulations and managing coverage development.

Experience Level

Senior; minimum of 8 years’ experience in circuit design and verification.

Responsibilities

The primary responsibilities include:

• Understanding the expected functionality of designs.
• Designing and developing verification environments.
• Improving the verification architecture and flow.
• Running RTL and gate-level simulations and regression.
• Developing and analyzing code/functional coverage.

Requirements

The role requires the following qualifications:

• Bachelor's or Master’s degree in Computer Science or Mechanical Engineering.
• Familiarity with System Verilog and UVM verification.
• Experience with test plans, test benches, assertions, and debugging designs.
• Self-managing and independent working skills.
• Knowledge of computer architecture and industry standard verification tools.
• Good IC verification skills and problem-solving abilities.
• Scripting and automation skills (Python) are a plus.
• Proficiency in C/C++/Java or similar programming languages is an advantage.
• Experience setting up large verification environments.
• Knowledge of DDR protocol and mixed-signal verification is a plus.

Education Requirements

Bachelor's degree or Master's degree in Computer Science or Mechanical Engineering.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.