Sr. Staff Physical Design Engineer

Job Title

Sr. Staff Physical Design Engineer

Role Summary

Lead physical implementation for advanced-node SoC designs from RTL to GDS within the Physical Design (SoC Integration) team. Drive synthesis, placement, CTS, routing, extraction, verification, and signoff while collaborating with front-end, DFT, power, and analog teams to optimize power, performance, and area (PPA).

Experience Level

Senior - typically requires 6+ years of hands-on ASIC physical design experience at a senior/lead level.

Responsibilities

Deliver and lead physical design work for high-performance blocks or full-chip SoC designs and mentor junior engineers.

• Lead physical implementation from synthesis through GDS for blocks or full-chip SoC designs at advanced process nodes (7nm, 5nm, 3nm).
• Execute and optimize synthesis, placement, clock tree synthesis (CTS), and routing using Synopsys ICC2/Fusion Compiler or Cadence Innovus.
• Drive timing closure and PrimeTime signoff, including multi-corner/multi-mode analysis, SI, AOCV/POCV, crosstalk analysis, and ECO implementation.
• Perform RC extraction using StarRC or Quantus and ensure correlation between extraction and STA results.
• Own physical verification signoff with Mentor/Siemens Calibre and resolve DRC, LVS, ERC, and antenna violations.
• Conduct power integrity analysis with Ansys RedHawk (static/dynamic IR drop and EM) and implement power grid and decap optimizations.
• Develop and maintain physical design flows and automation (Tcl, Perl, Python); mentor junior engineers and coordinate with cross-functional teams to meet tapeout schedules.

Requirements

Key must-have technical qualifications followed by preferred skills.

• Must-have: 6+ years of hands-on ASIC physical design experience with proven tapeout success.
• Must-have: Expert-level proficiency in synthesis, placement, CTS, and routing using Synopsys or Cadence P&R tools.
• Must-have: Deep knowledge of static timing analysis (STA) and PrimeTime signoff, including multi-corner/multi-mode closure.
• Must-have: Experience with physical verification using Calibre (DRC, LVS, ERC) and IR drop/EM analysis using RedHawk.
• Must-have: Hands-on experience with RC extraction tools (StarRC or Quantus) and ECO implementation.
• Nice-to-have: Experience at 5nm/3nm nodes with FinFET and multi-patterning design rules.
• Nice-to-have: Familiarity with low-power design techniques (UPF, clock gating, multi-Vt, voltage islands).
• Nice-to-have: Strong scripting/programming skills in Tcl, Perl, and Python for flow automation and data analysis.
• Nice-to-have: Experience leading or mentoring physical design teams; exposure to memory-centric interfaces (SSD SoC, HBM) or chiplet/D2D interconnects (UCIe) is a plus.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is required; Master's degree preferred.

About the Company

Company: SK hynix America

Headquarters: Icheon, South Korea

U.S. subsidiary of SK hynix, a global semiconductor company specializing in DRAM and NAND flash memory and related memory solutions for mobile devices, data centers, and consumer electronics. Focuses on advanced memory technologies, AI applications, and high-performance storage.