Sr. Staff Package Design Engineer - MIS substrate / FC exposed die (Power or GaN experience required)

Job Title

Sr. Staff Package Design Engineer - MIS substrate / FC exposed die (Power or GaN experience required)

Role Summary

Design and develop advanced package and interconnect solutions for power SiP/modules, wafer-level and flip-chip packaging, and multi-chip modules. Lead material, process and supplier (OSAT/CM) qualification and package qualification for consumer, industrial and automotive power applications.

Work with product, reliability, quality and operations teams to transfer designs into production, run DOEs, resolve process issues, and implement ramp monitoring and controls.

Experience Level

Senior — typically requires more than 10 years of relevant package development experience, especially with power SiP/modules, wafer-level and flip-chip packaging.

Responsibilities

Key responsibilities include technical leadership for package development, supplier qualification, process optimization, and production ramp:

• Benchmark, select and qualify materials, processes and OSATs/contract manufacturers.
• Develop and run DOE to optimize processes; establish process specifications and monitor process control.
• Work with OSAT/CM to resolve process issues early in production to ensure quality.
• Qualify new packages and processes with Product and Reliability teams within required timelines.
• Ensure smooth transition into production and implement ramp-up monitoring.
• Participate in packaging roadmap development and maintain technical expertise on power SiP/modules, wafer-level packaging, flip-chip interconnects and panel-level packaging.
• Establish and maintain package design rules and qualification plans for automotive, industrial and consumer power applications.
• Collaborate with Marketing, Product, Quality and Operations to address customer issues and support business growth.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• Extensive hands-on experience in package development emphasizing power SiP/modules, wafer-level and flip-chip packaging.
• Experience working with OSATs/CMs and executing DOEs to optimize assembly processes.
• Strong knowledge of assembly processes, qualification methods, SPC and statistical analysis tools.
• Proven ability to qualify packages and processes for production and to implement ramp monitoring.
• Strong interpersonal, communication, analytical and presentation skills; experience coordinating across cross-functional teams.
• Experience with packaging for power devices; GaN-related packaging experience is required or strongly preferred.
• Nice-to-have: familiarity with wire-bonding and multi-chip module technologies.

Education Requirements

Doctorate, Master’s or Bachelor’s degree in Physics, Chemistry, Mechanical, Electrical, or Materials Engineering.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.