Sr. Staff Formal Verification R&D Engineer

Role Summary

The Sr. Staff Formal Verification R&D Engineer will design and implement formal verification algorithms for VLSI chip designs, contributing to scalability and reliability in verification tools and collaborating on innovative solutions.

Experience Level

Senior level with 8-10 years of relevant experience.

Responsibilities

Key responsibilities include:

• Designing and implementing advanced formal verification algorithms and proof engines.
• Developing scalable, memory-efficient, and mathematically robust solvers.
• Integrating solutions into the Synopsys VC Formal platform.
• Collaborating with teams on extending formal verification technologies.
• Engaging with customers and industry partners on verification needs.
• Contributing to the formal verification community through publications and mentorship.

Requirements

Must-have skills and qualifications include:

• Expertise in formal methods, model checking, theorem proving, and equivalence checking.
• Strong proficiency in algorithms, data structures, and complexity analysis.
• Professional coding skills in C/C++ and experience developing large-scale software systems.
• Familiarity with hardware architecture and design languages like SystemVerilog.
• Peer recognition in the formal verification community.

Education Requirements

Information not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.