Sr Staff Formal Verification R&D Engineer

Job Title

Sr Staff Formal Verification R&D Engineer

Role Summary

The Sr Staff Formal Verification R&D Engineer will be part of Synopsys' Engineering team, focusing on formal verification processes and methodologies to ensure high-quality design. This role aims to enhance the productivity and effectiveness of the verification effort in chip design.

Experience Level

Senior level position. Experience requirements are not specified.

Responsibilities

The primary responsibilities include:

• Develop and implement formal verification methodologies.
• Collaborate with design teams for effective integration of verification tools.
• Conduct thorough analysis of system specifications and write verification plans.
• Mentor junior engineers and share best practices in formal verification.

Requirements

Applicants must meet the following criteria:

• Strong understanding of formal verification methodologies.
• Experience with hardware description languages (e.g. Verilog, VHDL).
• Proficiency in formal verification tools and software.
• Bachelor’s degree in Computer Science, Electrical Engineering, or a related field is preferred.
• Nice to have: experience in developing verification IP and working with RTL designs.

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related field is preferred.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.