Sr Staff Digital Engineer – Microcontroller (MCU) Systems & Architecture

Job Title

Sr Staff Digital Engineer – Microcontroller (MCU) Systems & Architecture

Role Summary

Senior technical leader on the General Purpose MCU Design and Architecture team. Lead specification, RTL implementation, physical synthesis, and full-chip verification for next-generation MCU platforms integrating RISC-V and ARM Cortex-M cores.

Define subsystem architecture, coordinate front-end and physical design hand-offs, and drive IP-to-chip verification and debugging.

Experience Level

Senior-level technical role. (No explicit years-of-experience stated.)

Responsibilities

Primary responsibilities include design, implementation, verification, and integration of MCU subsystems and related IP.

• Translate product requirements into target and detailed specifications for SYSSS, CPUSS, Peripheral IPs, IOTOP, and ChipTop.
• Implement RTL (Verilog/SystemVerilog) and provide implementation hand-off to MiddleEnd and BackEnd teams.
• Create and execute unit- and chip-level verification using UVM/SystemVerilog; author test plans and verification checklists.
• Lead root-cause debugging across IP, MCU, and SoC levels in RTL, simulation, and post-synthesis environments.
• Perform module-level physical synthesis and top-level technology checks (HLDRC, STA checks, DFT checks).
• Define and integrate subsystems around RISC-V and ARM Cortex-M; manage CDC and asynchronous transfer designs across clock/reset domains.
• Drive interconnect architecture and integration using AMBA protocols (AHB, APB, AXI).

Requirements

Must-have technical skills and domain knowledge required for the role.

• Hands-on RTL and verification: Verilog, SystemVerilog, SVA, UVM.
• Strong IP/MCU/SoC debugging experience across front-end, simulation, and post-synthesis flows.
• Deep understanding of RISC-V and ARM Cortex-M cores and common MCU peripherals (WDT, INTC, I2C, SPI, ADC).
• Expertise in AMBA bus protocols (AHB, APB, AXI) and CDC/asynchronous transfer techniques.
• Experience with EDA toolchains (Cadence, Synopsys) and tools such as Xcelium, VCS, SimVision, Verdi, Spyglass, Design Compiler, Formality, PrimeTime.
• Experience running physical synthesis and technology verification (HLDRC, STAcheck, DFTcheck).
• Proficiency in scripting and automation (Perl, Python) and embedded languages (C, C++) is expected.

Education Requirements

Not specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.