Sr. Staff Application Engineer - ECO Timing

Role Summary

This role involves overseeing technical challenges related to timing signoff and design closure within the semiconductor industry. The individual will engage with R&D and lead complex silicon chip projects, optimizing power, performance, and area (PPA) through innovative solutions.

Experience Level

6-8 years of relevant experience in the semiconductor industry, with a strong foundation in timing signoff and design closure disciplines.

Responsibilities

• Review and analyze customer and partner feedback to enhance product and solution performance.
• Collaborate with R&D to shape technical roadmaps, specifications, and validation processes.
• Diagnose, troubleshoot, and resolve complex technical issues for customer installations.
• Deploy product best practices and deliver technical training.
• Support customer project execution using Synopsys tools and solutions.
• Partner with customer technical managers and Sales to identify challenges and deliver solutions.
• Communicate product value and technical messaging to diverse audiences.

Requirements

• BS or MS in Electrical or Computer Engineering.
• Hands-on expertise with Place & Route (P&R), extraction, Static Timing Analysis (STA), and Engineering Change Order (ECO) tools.
• In-depth understanding of timing methodologies, parasitic annotation, and timing analysis for IC designs.
• Experience with physical design and optimizing PPA targets, especially on advanced technology nodes.
• Strong scripting skills in TCL, Perl, and other languages.
• Comprehensive understanding of ASIC design flow and VLSI principles.

Education Requirements

Bachelor's or Master's degree in Electrical or Computer Engineering.