Sr. Signal Integrity Engineer - Serdes, Satellites (Starlink)

Job Title

Sr. Signal Integrity Engineer - Serdes, Satellites (Starlink)

Role Summary

Lead signal- and power-integrity engineering for Starlink satellite payload hardware across the full product lifecycle, from silicon/package evaluation and stackup selection through PCB layout, qualification, and field troubleshooting.

This role is highly cross-functional and requires defining SI/PI processes, simulations, test methodologies, and lab capabilities used across the Starlink payload organization.

Experience Level

Senior engineer. Typical background: 5+ years industry experience designing circuits, electronic products, or hardware, with domain experience in high-speed digital channels and power integrity.

Responsibilities

Primary responsibilities include analysis, specification, verification, and support of SI/PI for satellite payload hardware.

• Specify, design, simulate, verify, qualify and troubleshoot SI and PI for advanced satellite hardware (high-speed SERDES, optoelectronics, memory interfaces, PDNs).
• Evaluate IP, package, and PCB stackups; derive top-level PCB material and channel specifications.
• Design and optimize transitions and channel structures from die-to-die and across package/PCB boundaries.
• Drive component selection and define PDN architecture for ASICs, FPGAs, and processors.
• Collaborate with RF, antenna, ASIC, packaging, mechanical, thermal, software, supply chain, and production teams to architect and validate new products.
• Lead root-cause analysis and fixes for issues found in PCB fabrication, PCBA test, or satellite integration.
• Establish best practices, simulation workflows, signoff criteria, test methodologies, and lab/equipment requirements for SI/PI work.

Requirements

Must-have technical skills and experience required to perform the role.

• 5+ years industry experience designing circuits, electronic products, or hardware (product lifecycle experience preferred).
• 2+ years using 3D EM and high-speed channel simulation tools (examples: CST, HFSS, ADS).
• 2+ years research or industry experience in high-speed digital design or power integrity.
• Practical experience with PDN design and troubleshooting for ASICs/SoCs/FPGAs.
• Experience specifying and validating high-speed channels and PCB materials.
• Strong cross-functional communication and documentation skills for defining processes and training others.
• ITAR eligibility: must be a U.S. citizen, U.S. lawful permanent resident (green card holder), refugee, asylee, or be eligible to obtain required U.S. Department of State authorizations. For more information see ITAR information.

Other requirements:

• Ability to work extended hours or weekends as needed for mission-critical deadlines.
• Occasional travel may be required.

Education Requirements

Required: Bachelor’s degree in Electrical Engineering, Computer Engineering, or Physics. Preferred: Master’s or PhD in Electrical Engineering or Computer Engineering with emphasis in electromagnetic theory, transmission-line theory, wireline transceivers, or power integrity.

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.