Sr Principal Design Engineer- Memory IP
Cadence Design SystemsRole Summary
The role involves high-performance memory IP architecture design, owning the IC micro-architecture, and developing power analysis platforms. The engineer will work on complex IC development projects in a collaborative team environment.
Experience Level
Senior level, with at least 8 years of experience for those with a BS degree or 6 years for MS degree holders.
Responsibilities
The responsibilities include:
- Designing high-performance memory IP architecture.
- Owning IC micro-architecture and timing budget.
- Developing power analysis platforms.
- Conducting logic design, simulation, synthesis, STA, and testing.
- Working with Verilog/SystemVerilog and simulation environments.
- Driving complex IC development projects.
Requirements
Must-have qualifications include:
- BS degree in electrical engineering or related field with 8+ years of applicable experience, or MS degree with 6+ years of applicable experience.
- Proficiency in Verilog/SystemVerilog.
- Experience in IC design for high-speed and low power.
- Strong communication skills in English.
- Experience on memory IP is desired.
Education Requirements
BS or MS degree in electrical engineering, microelectronics, or related field is required.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
