Sr. Principal Design Engineer
Join the semiconductor engineering team to design and develop SRAM and register-file circuits for low-power, low-voltage, high-performance applications. The role focuses on full-custom and compiler-based SRAM macro design, characterization, layout coordination, and silicon validation.
Senior β typically 6 to 18 years of relevant SRAM/VLSI/memory design experience.
Primary responsibilities include circuit design, simulation, layout coordination, and post-silicon validation.
Must-have skills and experience.
Nice-to-have: experience with FinFET process flows, compiler-based memory generation, or prior silicon bring-up and failure analysis.
B.Tech or M.Tech in Electrical Engineering, VLSI, or Microelectronics.
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
