Sr Principal Design Engineer
Cadence Design SystemsRole Summary
The Sr Principal Design Engineer role involves working in the VLSI domain with a focus on design methodologies and validation. The engineer will manage project schedules and deliverables independently while developing comprehensive testing frameworks.
Experience Level
Senior level with 12-14 years of experience in the VLSI domain.
Responsibilities
The responsibilities include:
- Expertise in Verilog, HVL (SV, Specman e), and UVM/OVM/eRM methodologies.
- Development and closure of assertions, constraint randomization, functional and code coverages, and formal verification.
- Test-bench development and managing RTL and GLS simulation debugging.
- Effective project schedule management and delivery oversight.
- Proficiency in Perl/Tcl scripting and automation.
Requirements
Must have the following skills and qualifications:
- Master’s or Bachelor’s degree in Engineering.
- Strong VLSI domain knowledge.
- Advanced skills in Verilog, HVL, UVM/OVM/eRM.
- Experience with assertions, constraint randomization, and debugging RTL/GLS simulations.
- Proficient in Perl/Tcl scripting.
Education Requirements
Master’s or Bachelor’s degree in Engineering is required.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
