The Sr Principal Application Engineer is responsible for supporting and leading customer projects related to the Cadence Digital Logic Verification platform, primarily in Vietnam and the Asia-Pacific region. The role involves working closely with the sales team to identify opportunities, manage technical evaluations, conduct trainings, and provide technical expertise to clients.
Senior, with a minimum of 8-10 years of industry experience depending on degree level.
Key responsibilities include:
Must-have requirements include:
Nice-to-have include knowledge of emulator/accelerators, SVA, JasperGold, scripting skills with Python/Perl, and familiarity with general interface protocols such as AMBA.
Bachelor's degree in Computer Science or Electrical Engineering is required, with a Master's degree being advantageous.
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
