Sr Mgr Validation Engineering

Role Summary

The Validation Manager is responsible for managing and cooperating with the team to validate and characterize products, focusing on delivering high-quality buffer chip products.

Experience Level

10+ years of industry experience in validation engineering, specifically with processor-memory interfaces, DDR topologies, and high-speed signaling.

Responsibilities

• Partner with internal and external cross-functional teams, including development engineers and procurement experts.
• Develop and improve validation methodologies to enhance coverage and reduce time-to-market.
• Collaborate with Design, Architecture, Verification, and Operations teams for high-quality product delivery.
• Manage bench validation team for executing validation and characterization of memory buffer chips.
• Engage in hands-on validation and software development for lab automation.

Requirements

• Bachelor's or MS in Electrical Engineering.
• Experience with DDR4/5 and high-speed memory interface simulation.
• Bench testing experience with ATE or system testing knowledge preferred.
• Proven track record in developing validation methodologies.
• Proficient in Python programming for validation automation and data analysis.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering required.