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Sr Manager, Physical Design

Renesas
March 11, 2026
Full-time
Remote friendly (Noida, Uttar Pradesh, India)
Worldwide
Level - Senior

Role Summary

We are seeking a Physical Design expert and manager with strong people and technical skills in Synthesis, UPF, VCLP, and LEC to join our semiconductor backend team. The role emphasizes RTL synthesis ownership, LEC closure, UPF development, and VCLP sign-off for complex SoC designs, collaborating closely with Physical Design, DFT, and Front-End teams.

Experience Level

Senior, requiring 10-15 years of relevant experience.

Responsibilities

The responsibilities include:

  • Complete understanding of RTL to GDS flow in the physical design cycle.
  • Collaborating, leading, and driving team members with quality and schedule in check, aligned to organizational needs.
  • Owning RTL synthesis from elaboration to final signoff.
  • Debugging design constraints and supporting DFT insertion through cross-team collaboration.
  • Handling multiple tasks and changing priorities from internal customers.
  • Deep debugging skills for logic equivalence checks (LEC) across RTL, synthesized, and ECO netlists.
  • Creating, maintaining, and debugging UPF, ensuring alignment with FE power intent.
  • Understanding, defining, and managing power domains and supporting low power signoff (VCLP/power checks).
  • Handling RTL ECOs during late design stages.
  • Automating flows using TCL scripting.
  • Leading by example technically with strong expertise in Physical Design.

Requirements

Required qualifications include:

  • 10+ years of hands-on experience in Physical Design for SoC designs.
  • Strong knowledge of RTL, synthesis optimization, and low-power design.
  • Hands-on experience with UPF creation and power-domain modeling.
  • Experience with tools like Cadence Genus, Synopsys Fusion Compiler, Conformal, and VCLP.
  • Strong TCL scripting skills (Perl/Python is a plus).

Preferred qualifications include:

  • Advanced node experience (7nm / 5nm or below).
  • Power-aware ECO experience.
  • Exposure to physical-aware synthesis and SoC-level UPF/VCLP closure.

Education Requirements

Not specified.


About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.

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Date Posted: 2026-03-11