Sr Engineer, Physical Design
RenesasJob Title
Sr Engineer, Physical Design
Role Summary
This role involves working as a Physical Design Engineer within the semiconductor backend team. The engineer will focus on various aspects of the physical design cycle including RTL synthesis, LEC closure, UPF development, and VCLP analysis for complex SoC designs.
Experience Level
Senior level, with a minimum of 5 years of experience in physical design.
Responsibilities
Key responsibilities include:
- Perform RTL synthesis from elaboration to final sign-off.
- Understand physical design cycles and inter-team communications.
- Debug logic equivalence checks (LEC) across different netlists.
- Create and maintain UPF while ensuring alignment with Front-End power intent.
- Conduct low power checks.
- Automate design flows using TCL scripting.
Requirements
Essential qualifications are:
- At least 2 years of hands-on experience in physical design for SoC designs.
- Familiarity with the synthesis process and low-power design methodologies.
- Experience in UPF creation and power-domain modeling.
- Tools familiarity: Cadence Genus, Stylus, Synopsys Fusion Compiler, Conformal, VCLP.
- Strong TCL scripting skills; proficiency in Perl/Python is an advantage.
Education Requirements
Not specified.
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
