Sr. ASIC Design Verification Engineer (Silicon Engineering)

Role Summary

The Sr. ASIC Design Verification Engineer will be responsible for digital ASIC verification at both block and system levels, developing next-generation ASICs for deployment in various environments. This role requires collaboration with cross-disciplinary teams and a focus on delivering innovative solutions for Starlink's performance and capabilities.

Experience Level

5+ years of experience in design verification and test bench development is required for this position.

Responsibilities

• Responsible for digital ASIC verification at block and system level.
• Write and review test plans, develop test harnesses and test sequences.
• Conduct test plan execution, run regressions with a focus on code and functional coverage closure.
• Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
• Act as a hands-on self-starter, executing necessary steps for complex digital design verification.

Requirements

• Education Requirements: Bachelor's degree in Electrical Engineering or Computer Engineering.

Preferred Skills and Experience

• Advanced degree in Electrical Engineering or Computer Engineering.
• Familiarity with verification methodologies such as UVM/OVM/VMM.
• Strong knowledge of object-oriented programming.
• Expertise in developing test plans and analyzing results.
• Experience with scripting languages for automation, e.g., Python.
• Knowledge of RTL design and chip bring-up.
• Ability to work in a dynamic environment with shifting requirements.

Additional Requirements

The candidate must be willing to work extended hours and weekends as needed.