Sr Account Technical Executive II

Job Title

Sr Account Technical Executive II

Role Summary

Senior technical customer-facing role driving adoption and deployment of Cadence Digital IC and Custom/Analog/ RF design flows, with primary focus on Innovus and Virtuoso platforms and signoff technologies. The role partners with customer design and CAD teams to improve layout productivity, quality, and time-to-market, and translates customer needs into actionable requirements for R&D and product engineering.

Experience Level

Senior — typically 5–10+ years of relevant industry experience in Custom IC, Analog, RF, or Digital IC design and layout engineering.

Responsibilities

Primary responsibilities include technical engagement, methodology leadership, and enabling customer success with Cadence tools and flows.

• Lead technical engagements across Digital IC, Custom IC, Analog, and RF design flows, focusing on Innovus and Virtuoso platforms and signoff technologies.
• Partner with customer design and CAD teams to optimize layout productivity, PPA, and time-to-market for tapeouts and SOC projects.
• Drive adoption of advanced capabilities: constraint-driven and automation-assisted layout, device-level and full-chip methodologies, and EM/IR-aware extraction flows.
• Champion integration of AI-driven design techniques, including agentic AI workflows and AI-assisted layout optimization and verification.
• Define methodology and flow improvements; provide technical leadership and best practices for large-scale deployment.
• Translate customer pain points into product and R&D requirements and influence competitive replacements and footprint expansion.
• Support executive-level discussions by linking technical value (PPA, productivity, risk reduction) to business outcomes.

Requirements

Must-have technical skills, platform experience, and customer engagement capabilities.

• Deep hands-on experience with Innovus and Virtuoso-based design environments and signoff flows (layout, DRC/LVS, extraction, post-layout verification).
• Experience across digital flows (Genus/Innovus, Quantus, Tempus, Pegasus) with a clear understanding of PPA trade-offs and full-stack flow interactions.
• Practical expertise in custom analog/mixed-signal layout techniques: device matching, symmetry, common-centroid, shielding, and parasitic-aware layout.
• Familiarity with Spectre simulation, layout-to-schematic integration, PCell development, layout automation, and scripting (SKILL preferred).
• Demonstrated experience working with large SOC tapeouts, foundry PDK enablement, DTCO, and advanced-node layout challenges (FinFET, GAA).
• Experience or strong interest in applying AI/ML to EDA workflows, including agentic AI frameworks and data-driven optimization approaches.
• Proven customer-facing experience: engage CAD teams and design leads, communicate technical details to executives, and drive alignment with product roadmaps.
• Ability to travel approximately 25%, primarily within North America.
• Nice-to-have: exposure to chiplet design flows, packaging, IP design, or technology entitlement activities.

Education Requirements

BSEE required; MSEE or higher strongly preferred. Degree focus on Electrical/Electronic Engineering or related technical disciplines (no equivalent-degree language specified).

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.