SPE Digital Verification Engineer

Role Summary

The role involves participating in pre-silicon RTL Verification activities related to PCIe Controller SoftIP development, focusing on PCI-Express and CXL controller technologies.

Experience Level

4-6 years of experience in HDL logic design and verification.

Responsibilities

• Testbench and test sequence development for verification of new controller technologies and features.
• Functional coverage planning, coverage item coding, and augmentation of the test suite to achieve Functional Coverage.
• Regression test development, monitoring, debugging, triage, and corrections to the test environment, sequences, and debug of controller RTL design.
• Development and support of Verification environment scripting and capabilities.

Requirements

• Bachelor's Degree or above in Electrical Engineering or Computer Science.
• Fluency in System Verilog / UVM testbench, Verilog/System Verilog logic design/RTL is a must.
• Experience with PCI-Express controller and protocol is required.
• Working knowledge of Python and TCL scripting languages is preferred.

Education Requirements

Bachelor's Degree or above in Electrical Engineering or Computer Science.