SOC Verification Lead Engineer

Role Summary

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, ensuring a bug-free final design.

Experience Level

8+ years of design verification experience is required.

Responsibilities

• Develop and maintain tests for functional verification at SOC level.
• Build testbench components to support the next generation IP.
• Maintain or improve current verification libraries to support SOC/Full-chip level verification.
• Provide technical support to other teams.
• Assist the Hardware emulation team in porting the RTL to Palladium/Zebu or HAPS/Protium platforms.

Requirements

• Strong familiarity with verification methodologies such as OVM, UVM, or VMM.
• Familiarity with Verilog and general logic design concepts.
• Knowledge of system-level architecture including buses (AXI/AHB), bridges, and memory controllers (DDR4/DDR5).
• Strong working knowledge of the UNIX environment and scripting languages like Perl or Python.
• Excellent waveform debug skills using industry-standard design tools such as VCS, NCSIM/XCELIUM, Verdi, QUESTASIM.
• Experience with UNIX revision control tools (ICM manage, CVS, Perforce) and bug tracking tools (JIRA).
• Experience in verifying multimillion-gate chip designs from specifications to tape-out.
• Excellent communication and presentation skills.
• Ability to work collaboratively with cross-functional teams.
• Familiarity with processors and boot flow is advantageous.
• Familiarity with software development flow (assembly and C) is a benefit.

Education Requirements

• BS/MS in Electrical Engineering (EE), Computer Engineering (CE), or Computer Science (CS).