SOC Verification Engineer

Role Summary

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, ensuring no bugs in the final design.

Experience Level

8+ years of design verification experience.

Responsibilities

Key responsibilities include:

• Develop and maintain tests for functional verification at SOC level.
• Build testbench components to support the next generation IP.
• Maintain or improve current verification libraries to support SOC/Full-chip level verification.
• Provide technical support to other teams.
• Assist the Hardware emulation team in porting the RTL to Palladium/Zebu or HAPS/Protium platforms.

Requirements

Candidates should possess strong familiarity with Verification Methodologies such as OVM, UVM, or VMM, and be well-versed in Verilog and General Logic Design concepts. Other requirements include:

• Knowledge of system-level architecture including AXI/AHB, DDR4/DDR5 memory controllers, USB, PCIe, and Ethernet.
• Strong working knowledge of UNIX environment and scripting languages (Perl, Python).
• Excellent waveform debug skills using industry standard design tools like VCS, NCSIM/XCELIUM, Verdi, QUESTASIM.
• Experience with UNIX Revision Control tools (ICM manage, CVS, Perforce) and bug tracking tools (JIRA).
• Proficiency in verifying multimillion gate chip designs from specifications to tape-out.
• Excellent communication and presentation skills.
• Ability to work with cross-functional teams.
• Familiarity with processor boot flow and software development flow (assembly and C) is advantageous.

Education Requirements

BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.