SOC Verification Engineer - CLK RST & Power Management

Role Summary

The SOC Verification Engineer will be responsible for the verification of clock and reset management, as well as power gating across SoCs. The role includes coordinating with the design team for UPF delivery and collaborating with the testbench team to establish the necessary infrastructure for testing and simulation.

Experience Level

This position requires 5 to 10 years of experience in digital verification, specifically in clock and reset verification, power management, and related SOC verification activities.

Key Responsibilities

The responsibilities of this position include:

• Manage the verification process for CLK, RST, and power management within the SOC.
• Create testbench collaterals necessary for verification.
• Coordinate between design and verification teams to ensure quality UPF delivery.
• Work closely with power architects to address simulation issues.

Requirements

Candidates must possess strong problem-solving skills and effective communication abilities. Expertise in SOC verification, system-level architectures, and familiarity with tools such as UVM, System Verilog, and other design/verification methodologies is essential.

Education Requirements

A degree in Electrical Engineering (BE/B.Tech/ME/MTech/MS) or equivalent in ECE/EEE/CSE is required.